Riviera-PRO - Functional Verification - Products - Aldec
Description
pulled from site's meta descriptionAldec, Inc. Riviera-PRO is the industry-leading comprehensive design and verification platform for complex SoC and FPGA devices. Riviera-PRO enables the ultimate verification environment (Testbench) productivity, reusability, and automation, by combining the high-performance multi-language simulation engine, advanced debugging capabilities at different levels of abstraction (TLM, RTL, and Gate-Level), and support for the latest Language (VHDL, Verilog, SystemVerilog, SystemC) and Verification Library (OVM, UVM, VMM) Standards.
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Categories:
- AboutUs AutoGen
- ASIC
- FPGA
- SOC
- Simulation
- Co-Simulation
- Verification
- Validation
- Performance
- Debugging
- Debug
- Mixed-Language
- HDL
- VHDL
- Verilog
- PLI
- VHPI
- DPI
- SystemVerilog
- SV
- SystemC
- SVA
- PSL
- OVA
- OpenVera
- Standard
- Interoperability
- IEEE
- 1076-1993
- 1076-2002
- 1076-2008
- 1364-1995
- 1364-2001
- 1364-2005
- 1800-2009
- 1666-2005
- 1850-2005
- P1735
- Accellera
- UVM
- OVM
- VMM
- OS-VVM
- VVM
- EDIF
- SDF
- Matlab
- Simulink
- IP
- SecureIP
- AXI
- Spartan
- Virtex
- Zynq
- Stratix
- Cyclone
- ProASIC
- Denali
- ASDB
- ACDB
- FSDB
- VCD
- TCL
- Coverage
- Covergroup
- Assertions
- Profiler
- Dataflow
- X-Trace
- Regression
- Automation
- ESL
- TLM
- RTL
- Netlist
- RDSN
- RWSP
- AWC
- LV
- LVT
- LVT-SV